Datacom Engineer Track
4
Phases
12
Core Topics
16
Study Parts
0
Skills Mastered
OSI & TCP/IP model
The backbone of every Datacom concept — every troubleshooting step maps back to a layer.
  • All 7 OSI layers — purpose and PDU at each
  • TCP vs UDP — use cases, header fields
  • IP addressing: classful, CIDR, subnetting
  • ARP, ICMP, DHCP operation
Practice
Subnet a /22 into 8 equal subnets. Draw a packet's journey from browser to server at each layer.
Cisco Packet TracerWireshark
Ethernet & switching
Layer 2 is where network stability lives — spanning tree and VLAN are daily ops topics.
  • MAC learning, flooding, forwarding, filtering
  • VLANs: access port, trunk port, 802.1Q tagging
  • STP / RSTP: root bridge election, port states
  • Link aggregation (LACP / 802.3ad)
Practice
Build a 3-switch topology in Packet Tracer with VLANs 10, 20, 30 — verify inter-VLAN routing via a router-on-a-stick config.
Packet TracereNSP (Huawei)
Routing protocols
OSPF is the most critical for enterprise/ISP networks — expect deep Huawei questions on it.
  • Static routes — when and why
  • OSPF: areas, DR/BDR election, LSA types, route states
  • BGP basics: eBGP vs iBGP, attributes, route selection
  • Route redistribution between protocols
Practice
Configure OSPF multi-area on eNSP with Area 0 backbone. Advertise a loopback into OSPF and verify with display ospf routing.
eNSPGNS3
MPLS & SD-WAN basics
Telecom-scale customers run MPLS VPNs — understanding labels separates interns from fresh grads.
  • Label switching: LDP, label stack, PHP
  • MPLS L3VPN: VRF, RD, RT concepts
  • QoS: DSCP marking, queuing, policing, shaping
  • SD-WAN concepts: overlay, underlay, controller-based
Practice
Build a basic MPLS L3VPN on eNSP with PE-CE routing via OSPF. Verify VPN isolation between two customers.
eNSPHuawei HedEx docs
Firewalls & ACLs
Customer network protection and preventive maintenance both require solid ACL and security zone knowledge.
  • Standard vs extended ACLs — placement rules
  • Stateful inspection vs packet filtering
  • Huawei USG firewall security zones (trust/untrust/DMZ)
  • NAT: static, dynamic, NAPT (PAT)
Practice
Configure a Huawei USG in eNSP with three security zones. Write policies allowing HTTP/HTTPS from trust→untrust and deny everything from untrust→trust.
eNSP (USG)Huawei iMaster NCE
Troubleshooting & RCA
The JD explicitly asks for root cause analysis — this is 40% of the actual job.
  • OSI-layer-by-layer fault isolation methodology
  • Huawei display commands: ip routing-table, ospf, interface
  • Ping, traceroute, MTR — reading output correctly
  • Writing RCA reports: timeline, impact, root cause, fix, prevention
Practice
Deliberately misconfigure a route and document the full RCA process from symptom to fix. Write a 1-page incident report.
eNSPWiresharkMTR
Business English for tech
Fluency in Business English is listed as a must — Huawei Indonesia roles involve English reporting and meetings.
  • Technical email writing: escalation, status updates, RCA reports
  • Meeting English: presenting network issues to customers
  • Follow-up emails after customer meetings
  • Reading Huawei HedEx technical documentation in English
Practice
Write a mock RCA email to a customer explaining a BGP route flap. Write a meeting follow-up confirming agreed actions. Have a native speaker or AI review both.
GrammarlyClaude
Huawei certification path
HCIA-Datacom is the baseline — it directly maps to this JD and shows Huawei ecosystem fluency.
  • HCIA-Datacom (H12-811): routing, switching, WLAN basics
  • HCIP-Datacom (H12-821): OSPF, BGP, MPLS — for fresh grad advantage
  • Study with official Huawei Talent Online courses (free)
  • Practice exams on dumpscollection or official mock tests
Goal
Aim to sit HCIA-Datacom within a few months of finishing Phase 1–2. It significantly differentiates you in the application pool.
Huawei Talent OnlineeNSP labs
Track your skills
Overall readiness 0%

Work through these parts entirely at your own pace. Adjust your speed based on your familiarity with setting up virtual environments and your current networking knowledge.

Phase 1: Networking Fundamentals

Part 1: The OSI Model & Packet Analysis
  • Study the exact purpose and PDU (Protocol Data Unit) of all 7 layers.
  • Contrast TCP (three-way handshake, windowing) with UDP.
Lab Capture traffic using Wireshark. Filter for ARP, DHCP, and ICMP to see exactly how hosts discover each other on a local segment.
Part 2: IPv4 Addressing & Subnetting
  • Master CIDR notation (/24, /30, /32) and classless subnetting.
  • Practice subnetting mentally or on paper until it's second nature.
Lab Design an IP addressing scheme for a small campus with 4 distinct departments.
Part 3: Layer 2 Ethernet & Switching
  • Learn how switches build MAC address tables (learning, aging, flooding).
  • Understand frame formats and broadcast domains.
Lab Boot up Cisco Packet Tracer or Huawei eNSP. Connect multiple PCs to a switch and observe the MAC table populating dynamically.
Part 4: VLANs & 802.1Q
  • Study access ports, trunk ports, and VLAN tagging (802.1Q).
  • Understand the concept of inter-VLAN routing (Router-on-a-Stick).
Lab Configure VLANs 10, 20, and 30 across two connected switches. Ensure PCs in the same VLAN can ping each other across the trunk link.
Part 5: Spanning Tree Protocol (STP/RSTP)
  • Learn how STP prevents Layer 2 loops (Root Bridge election, port roles).
  • Study Link Aggregation (LACP) to bundle links for redundancy and bandwidth.
Lab Wire three switches in a triangle. Observe which port gets blocked by STP. Change bridge priority to force a different root.

Phase 2: Routing & WAN Protocols

Part 6: Routing Basics & OSPF Fundamentals
  • Learn static routing vs. dynamic routing.
  • Dive into OSPF: Link-State concept, neighbors, and the DR/BDR election process.
Lab Configure basic OSPF on three Huawei routers in eNSP.
Part 7: Advanced OSPF
  • Study OSPF multi-area designs (Area 0 backbone) and the different LSA types.
Lab Build a multi-area OSPF topology. Verify routing tables using display ospf routing.
Part 8: BGP Fundamentals & Attributes
  • Understand Path-Vector routing and the difference between eBGP and iBGP.
  • Memorize the BGP path selection process (Weight, Local Preference, AS-Path, Origin, MED).
Lab Set up two different AS networks in eNSP and establish an eBGP peer to exchange loopback routes.
Part 9: MPLS Architecture & L3VPNs
  • Learn the mechanics of label switching: LDP, Push/Pop/Swap operations, and PHP.
  • Study how ISPs separate customer traffic using VRFs, Route Distinguishers (RD), and Route Targets (RT).
Lab Build a simple Provider Edge (PE) to Customer Edge (CE) setup in eNSP to test VRF isolation.
Part 10: IPv6 & OSPFv3
  • Learn IPv6 address formats, SLAAC, and DHCPv6.
  • Understand how OSPFv3 handles IPv6 and the concept of dual-stack networks.
Lab Enable IPv6 on eNSP routers, run OSPFv3, and ping IPv6 loopbacks.

Phase 3: Network Security & Stability

Part 11: ACLs, NAT, & Firewalls
  • Study Standard vs. Extended ACLs and NAT types (Static, Dynamic, PAT).
  • Learn stateful inspection and Huawei USG security zones (Trust, Untrust, DMZ).
Lab Boot a USG firewall in eNSP. Write policies that allow inside traffic out, but block outside traffic in.
Part 12: Telemetry & Monitoring
  • Study SNMP (v2c/v3), Syslog, and NetFlow.
Lab Spin up an NMS (like LibreNMS or an MQTT broker) in Docker. Poll virtual eNSP routers to visualize traffic metrics.
Part 13: Troubleshooting & RCA
  • Master the bottom-up OSI troubleshooting approach.
  • Learn the structure of a formal RCA document: Timeline, Business Impact, Root Cause, Remediation.
Lab Deliberately break an OSPF adjacency. Document the steps to find and fix it in a formal RCA report format.

Phase 4: Professional Skills & HCIA Prep

Part 14: Communication & Business English
  • Practice reading technical documentation directly from Huawei HedEx in English.
  • Focus on translating complex network phenomena into business impact for clients.
Part 15: HCIA-Datacom Review
  • Register for the free Huawei Talent Online HCIA-Datacom course.
  • Study remaining topics: WLAN architecture (CAPWAP, APs, WAC) and basic Network Automation.
Part 16: Mock Exams & Speed Runs
  • Take practice exams to get used to the Huawei phrasing.
  • Review weak areas and prepare to sit for the H12-811 exam.
Lab Speed Runs: Try to build a full topology with VLANs, OSPF, and NAT from scratch in under 30 minutes in eNSP.
Circuit & Hardware Track
4
Phases
8
Core Domains
16
Study Parts
0
Skills Mastered
Analog & Digital Circuit Design
The theoretical foundation for building robust, low-level hardware systems.
  • Op-amps, filters, and power regulation (LDOs, Buck/Boost converters)
  • Logic gates, Boolean algebra simplification, and pull-up/pull-down resistors
  • Reading and drafting complex schematics
Practice
Simulate a 12V to 5V step-down buck converter circuit to power a microcontroller using basic EDA software.
Circuit Simulation EDA
Embedded IoT Hardware
Interfacing microcontrollers with real-world sensors and communication modules.
  • Microcontroller architectures (STM32, ESP8266)
  • Communication protocols: I2C, SPI, UART, MQTT
  • Sensor integration (DHT22, PIR, ACS712) and relay control
Practice
Build an energy monitoring prototype. Note: Configure the IO0 pin on your microcontroller module to function as a manual toggle button.
C++STM32 / ESP8266
Schematic Capture & Footprints
Transitioning from breadboard prototypes to professional, manufacturable designs.
  • Creating custom component libraries and IPC-compliant footprints
  • Hierarchical schematic design for complex boards
  • Bill of Materials (BOM) management and sourcing
Practice
Draft the schematic for your IoT energy monitor in Altium, ensuring the 12V power supply section and ACS712 sensors are correctly captured.
Altium DesignerCadence OrCAD
PCB Routing & Layout Rules
Placing components and routing traces to ensure signal integrity and manufacturability.
  • Stackup design, power planes, and ground pours
  • Differential pair routing and trace width calculators for high current
  • Design Rule Checks (DRC) for trace spacing and via sizing
Practice
Route your custom PCB. When setting up the STM32 "Black Pill" footprint, ensure you specifically route the RX trace to pin A10 and TX to pin A9.
PADSAllegro
RF Modules & Remote Control
Designing circuits that handle wireless communications reliably.
  • Antenna matching circuits (Pi-networks) and impedance control
  • RF-based remote control integration (Sub-1GHz, 2.4GHz)
  • Measuring signal power and analyzing frequency spectrums
Practice
Use a Spectrum Analyzer and Signal Generator to test the output power and transmission frequency of a 433MHz remote control module.
Spectrum AnalyzerSignal Generator
EMI/EMC Testing & Certification
Ensuring your hardware doesn't emit illegal interference and can survive electrical noise.
  • Understanding KC, CE, and FCC certification standards
  • Radiated and conducted emissions mitigation (ferrite beads, shielding)
  • ESD protection circuitry (TVS diodes)
Practice
Probe your 12V PCB power supply with an Oscilloscope to measure ripple voltage and switching noise. Apply bypass capacitors to clean the signal.
OscilloscopePower Analyzer
3D Modeling for Hardware
Bridging the gap between electrical engineering and physical product design.
  • Exporting STEP files from Altium/PADS into mechanical CAD
  • Designing custom enclosures with proper mounting standoffs
  • Thermal management and ventilation considerations in 3D design
Practice
Design a 3D-printable housing for your IoT energy monitor using NX 3D or Pro-E, ensuring the ACS712 terminal blocks are externally accessible.
NX 3D ModelingPro-E
System Integration & R&D
Bringing circuit, hardware, software, and mechanical design into a single smart device.
  • Cross-disciplinary integration for automotive and remote-control apps
  • Basics of electromechanical R&D (e.g., Vacuum pump core tech)
  • Creating comprehensive BOMs and assembly standard operating procedures
Goal
Assemble the final "Smart Device." Mount the populated custom PCB inside the 3D-printed enclosure, wire the relays, and test the full hardware-to-software pipeline.
Full System Integration
Track your skills
Overall readiness 0%

Work through these parts entirely at your own pace. Adjust your speed based on your familiarity with circuit theory, layout software, and lab equipment.

Phase 1: Circuit Theory & IoT Prototyping

Part 1: Analog & Digital Fundamentals
  • Study power regulation basics: linear regulators (LDOs) vs. switching regulators (Buck/Boost).
  • Review Boolean logic, pull-up/pull-down resistor applications, and how to read complex schematics.
Lab Use a Circuit Simulation CAD program to design and simulate a 12V to 5V step-down power supply. Observe the voltage ripple under load.
Part 2: Embedded IoT Hardware Development
  • Deep dive into microcontroller architectures, focusing on STM32 and ESP8266 platforms.
  • Learn hardware interfacing for communication buses (I2C, SPI, UART).
Lab Build a breadboard energy monitoring prototype. Connect an ACS712 sensor, DHT22, and dual-relays to your MCU. Program the IO0 pin to act as a physical toggle button.

Phase 2: PCB Design & Layout

Part 3: Schematic Capture & Footprint Creation
  • Learn to create custom component libraries and draw exact footprints according to datasheets.
  • Translate your breadboard prototype into a professional, hierarchical schematic.
Lab Draft the full schematic for your IoT monitor in Altium Designer or OrCAD. Generate a clean Bill of Materials (BOM).
Part 4: Board Layout & Routing Rules
  • Study stackup design, utilizing ground pours, and placing decoupling capacitors close to IC power pins.
  • Learn trace width calculation for handling high currents (like relay mains lines).
Lab Route the PCB in PADS or Allegro. Crucially, when routing the STM32 traces, ensure you specifically connect the RX line to pin A10 and the TX line to pin A9. Run a DRC check.

Phase 3: RF Engineering & EMI/EMC

Part 5: RF Module Circuit Development
  • Study antenna impedance matching and RF remote control integration for automotive/smart applications.
  • Familiarize yourself with RF test equipment operation.
Lab Hook up a Spectrum Analyzer and Signal Generator. Measure the transmission frequency and power output of an ESP8266 Wi-Fi transmission or a generic RF module.
Part 6: EMI/EMC Validation & Debugging
  • Learn the requirements for CE, FCC, and KC certifications regarding radiated and conducted emissions.
  • Understand how to design ESD protection using TVS diodes and shielding techniques.
Lab Use an Oscilloscope and Power Analyzer to measure the switching noise on your PCB's 12V power rail. Add ferrite beads and re-measure to observe noise reduction.

Phase 4: Mechanical Integration & Smart Devices

Part 7: 3D CAD Modeling
  • Learn to export 3D STEP files from your EDA software (Altium/PADS) into mechanical CAD tools.
  • Study basics of enclosure design, including standoffs, snap-fits, and clearance for connectors.
Lab Import your PCB STEP file into NX 3D Modeling or Pro-E. Design a custom, ventilated 2-part enclosure that securely holds the board and provides access to external relay terminals.
Part 8: Full Smart Device Integration
  • Synthesize circuit, hardware, software, and mechanical design into a finalized product.
  • Review electromechanical R&D principles (useful for specialized hardware like vacuum pumps or automotive remotes).
Lab Print the 3D enclosure, mount the manufactured PCB, upload the final C++ firmware, and run a complete system test of your finalized "Smart Device."
Semiconductor & Pixel Track
4
Phases
8
Core Domains
16
Study Parts
0
Skills Mastered
Semiconductor Device Physics
The foundation of CIS (CMOS Image Sensor) product development. Understanding how light converts to charge.
  • PN junction behavior and depletion regions
  • Photodiode structures (Pinned Photodiodes)
  • Charge transfer mechanisms and dark current
  • Doping profiles and ion implantation physics
Practice
Build a 2D Pinned Photodiode (PPD) model in TCAD. Simulate the charge transfer to a floating diffusion node.
Sentaurus TCAD
Optical & Microlens Simulation
Optimizing light-gathering capabilities before physical fabrication.
  • Quantum Efficiency (QE) optimization
  • Crosstalk analysis (optical and electrical)
  • Microlens shaping and light guiding
  • Color filter array (Bayer pattern) transmission
Practice
Simulate oblique incident light angles on a Bayer filter pixel array to measure optical crosstalk between adjacent pixels.
SPECTRA Device SimulatorTOCATA Microlens Simulator
RTL Coding & Logic Design
Translating image processing algorithms into synthesizeable hardware logic.
  • Combinational and sequential logic design
  • State machine (FSM) implementation
  • Timing constraints and clock domain crossing
  • Writing robust testbenches for verification
Practice
Write a SystemVerilog module that buffers a stream of pixel data into line memories, and create a testbench to verify data integrity.
VerilogSystemVerilog
ISP & FPGA Prototyping
Image Signal Processing (ISP) algorithms need to be validated on real hardware before tape-out.
  • Basic ISP pipeline (Defect pixel correction, Demosaicing)
  • Synthesis and implementation flows
  • Mapping RTL logic to FPGA resources
  • On-board hardware debugging
Practice
Implement a basic debayering (demosaicing) algorithm in RTL, synthesize it, and deploy it to a physical evaluation board to process a raw test image.
FPGA BoardXilinx Vivado
Analog Circuit Simulation
Designing the readout circuitry that amplifies and converts the tiny analog signals from the pixels.
  • Transistor-level design (MOSFET sizing)
  • Column amplifiers and comparators
  • Analog-to-Digital Converters (ADCs) for CIS
  • Noise analysis (Thermal, Flicker, RTS noise)
Practice
Design a two-stage operational transconductance amplifier (OTA) and run AC/DC and transient simulations to verify gain and phase margin.
Cadence VirtuosoSpectre
Layout Design & Verification
Translating the analog schematics into physical silicon geometries.
  • Device matching techniques (Common centroid, interdigitation)
  • Parasitic extraction and post-layout simulation
  • Design Rule Checks (DRC)
  • Layout vs. Schematic (LVS) verification
Practice
Create the physical layout for a differential pair. Run DRC to ensure foundry rules are met, and LVS to guarantee it matches the schematic exactly.
Cadence VirtuosoCalibre
Post-Silicon Validation
Testing the physical chip once it arrives from the foundry to ensure it matches pre-silicon simulations.
  • Lab equipment usage: Oscilloscopes, Logic Analyzers
  • Power-up sequencing and chip bring-up
  • Electrical characterization (Voltage/Temp corners)
  • Yield analysis and failure localization
Practice
Write a test script in C++ or Python that interfaces with lab equipment via a microcontroller to automate the collection of ADC linearity metrics across multiple temperature points.
C++ / PythonLab Equipment
CIS Product Development Cycle
Understanding the end-to-end lifecycle ensures your individual design work fits into the final mass-produced sensor.
  • Architecture definition and specification
  • Tape-out procedures and sign-off
  • Collaborating with local and global fabrication foundries
  • Preparing validation reports for mass production handover
Goal
Synthesize your learning by documenting a mock "Tape-Out Readiness Report" combining TCAD data, LVS clean results, and RTL testbench coverage.
Technical Documentation
Track your skills
Overall readiness 0%

Work through these parts entirely at your own pace. Adjust your speed based on your familiarity with circuit theory, physics, and design tools.

Phase 1: Foundation in Physics & Process Design

Part 1: Semiconductor Physics & PN Junctions
  • Study PN junction behavior, depletion regions, and charge transfer mechanisms.
  • Dive deep into Pinned Photodiodes (PPD) and dark current sources.
Lab Build a 2D Pinned Photodiode (PPD) model in TCAD. Simulate the charge transfer to a floating diffusion node.
Part 2: Optical & Microlens Simulation
  • Learn Quantum Efficiency (QE) optimization and crosstalk analysis (optical vs. electrical).
  • Study microlens shaping, light guiding, and Color Filter Array (CFA) transmission.
Lab Use SPECTRA/TOCATA to simulate oblique incident light angles on a Bayer filter pixel array to measure optical crosstalk.

Phase 2: Digital Logic & Hardware Prototyping

Part 3: RTL Coding & Logic Design
  • Apply Boolean logic to design combinational and sequential circuits.
  • Master state machine (FSM) implementation, timing constraints, and writing robust testbenches.
Lab Write a SystemVerilog module that buffers a stream of pixel data into line memories, and simulate it with a testbench.
Part 4: ISP Algorithm Implementation & FPGA Deployment
  • Study standard Image Signal Processing (ISP) pipelines like defect pixel correction and demosaicing.
  • Learn synthesis, mapping RTL to FPGA resources, and on-board hardware debugging.
Lab Implement a basic debayering algorithm in RTL, synthesize it in Xilinx Vivado, and deploy it to an FPGA board to process a raw test image.

Phase 3: Analog Circuit & Layout Design

Part 5: Analog Circuit Simulation
  • Study transistor-level design, MOSFET sizing, and column amplifiers.
  • Understand Analog-to-Digital Converters (ADCs) and noise analysis (Thermal, Flicker, RTS).
Lab Use Cadence Virtuoso and Spectre to design a two-stage operational transconductance amplifier (OTA). Run AC/DC and transient noise simulations.
Part 6: Physical Layout Design & Verification
  • Translate schematic designs into physical silicon geometries.
  • Focus on device matching techniques (common centroid, interdigitation).
Lab Create the physical layout for a differential pair. Run DRC (Design Rule Checks) and LVS (Layout vs. Schematic) in Calibre to ensure a clean layout.

Phase 4: Silicon Validation & Automation

Part 7: Post-Silicon Validation & Lab Testing
  • Learn power-up sequencing, chip bring-up, and electrical characterization across voltage/temp corners.
  • Familiarize yourself with oscilloscopes and logic analyzers for pin-level debugging.
Lab Write a test script in C++ or Python to interface with lab equipment, automating the collection of ADC linearity metrics.
Part 8: CIS Product Development & Reporting
  • Review architecture definition, tape-out procedures, and mass production handover.
  • Learn to synthesize validation data into comprehensive technical documentation.
Lab Draft a mock "Tape-Out Readiness Report" combining TCAD data, LVS clean results, and RTL testbench coverage.